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ISL12027 数据表(PDF) 2 Page - Intersil Corporation

部件名 ISL12027
功能描述  Real Time Clock/Calendar with EEPROM
Download  28 Pages
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

ISL12027 数据表(HTML) 2 Page - Intersil Corporation

  ISL12027_10 Datasheet HTML 1Page - Intersil Corporation ISL12027_10 Datasheet HTML 2Page - Intersil Corporation ISL12027_10 Datasheet HTML 3Page - Intersil Corporation ISL12027_10 Datasheet HTML 4Page - Intersil Corporation ISL12027_10 Datasheet HTML 5Page - Intersil Corporation ISL12027_10 Datasheet HTML 6Page - Intersil Corporation ISL12027_10 Datasheet HTML 7Page - Intersil Corporation ISL12027_10 Datasheet HTML 8Page - Intersil Corporation ISL12027_10 Datasheet HTML 9Page - Intersil Corporation Next Button
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2
FN8232.8
August 12, 2010
Pin Descriptions
PIN NUMBER
SYMBOL
BRIEF DESCRIPTION
SOIC
TSSOP
1
3
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.
2
4
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal.
3
5
RESET
RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period
has expired or that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW
output. Recommended value for the pull-up resistor is 5k
Ω. If unused, connect to ground.
4
6
GND
Ground.
5
7
SDA
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an
open drain output and may be wire OR’ed with other open drain or open collector outputs.
6
8
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
71
VBAT
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event
that the VDD supply fails. This pin should be tied to ground if not used.
82
VDD
Power Supply.
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
VBAT TRIP POINT
(V)
BSW BIT DEFAULT
SETTING
VRESET
VOLTAGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL12027IB27Z
12027 IB27Z
VDD < VBAT
BSW = 1
2.63
-40 to +85
8 Ld SOIC
M8.15
ISL12027IB27AZ
12027 IB27AZ
VDD < VBAT
BSW = 1
2.92
-40 to +85
8 Ld SOIC
M8.15
ISL12027IB30AZ
12027 IB30AZ
VDD < VBAT
BSW = 1
3.09
-40 to +85
8 Ld SOIC
M8.15
ISL12027IBZ
12027 IBZ
VDD < VBAT
BSW = 1
4.38
-40 to +85
8 Ld SOIC
M8.15
ISL12027IBAZ
12027 IBAZ
VDD < VBAT
BSW = 1
4.64
-40 to +85
8 Ld SOIC
M8.15
ISL12027IV27Z
2027 I27Z
VDD < VBAT
BSW = 1
2.63
-40 to +85
8 Ld TSSOP
M8.173
ISL12027IV27AZ
2027 27AZ
VDD < VBAT
BSW = 1
2.92
-40 to +85
8 Ld TSSOP
M8.173
ISL12027IV30AZ
2027 30AZ
VDD < VBAT
BSW = 1
3.09
-40 to +85
8 Ld TSSOP
M8.173
ISL12027IVZ
2027 IVZ
VDD < VBAT
BSW = 1
4.38
-40 to +85
8 Ld TSSOP
M8.173
ISL12027IVAZ
2027 IVAZ
VDD < VBAT
BSW = 1
4.64
-40 to +85
8 Ld TSSOP
M8.173
ISL12027AIB27Z
12027A IB27Z
VDD < VBAT
BSW = 0
2.63
-40 to +85
8 Ld SOIC
M8.15
ISL12027AIV27Z
2027A I27Z
VDD < VBAT
BSW =0
2.63
-40 to +85
8 Ld TSSOP
M8.173
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12027, ISL12027A. For more information on MSL please see
techbrief TB363.
ISL12027, ISL12027A


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