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KM681000BLRE-10L 数据表(PDF) 9 Page - Samsung semiconductor

部件名 KM681000BLRE-10L
功能描述  128K x8 bit Low Power CMOS Static RAM
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制造商  SAMSUNG [Samsung semiconductor]
网页  http://www.samsung.com/Products/Semiconductor
标志 SAMSUNG - Samsung semiconductor

KM681000BLRE-10L 数据表(HTML) 9 Page - Samsung semiconductor

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PRELIMINARY
Revision 0.3
KM681000B Family
CMOS SRAM
April 1996
Address
CS1
Data Valid
CS2
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE (2)
(CS2 Controlled)
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of low CS1, high CS2 and low WE. A write begins at the latest transition among CS1 going low, CS2 going high and WE
going low. A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the beginning or write
to the end of write.
2.
tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3.
tAS is measured from the address calid to the beginning of write.
4.
tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at CS1, or WE going high, tWR2 applied in case a write
ends at CS2 going to low.
FUNCTIONAL DESCRIPTION
* X means don't care
CS1
CS2
WE
OE
Mode
I/O Pin
Current Mode
H
X
X
X
Power Down
High-Z
ISB,ISB1
X
L
X
X
Power Down
High-Z
ISB,ISB1
L
H
H
H
Output Disable
High-Z
ICC
L
H
H
L
Read
Dout
ICC
L
H
L
X
Write
Din
ICC
tWC
tCW(2)
tWR2(4)
tAW
tWP(1)
tDW
tDH
tAS(3)
tCW(2)


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