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KM6264BLGI-10 数据表(PDF) 9 Page - Samsung semiconductor |
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KM6264BLGI-10 数据表(HTML) 9 Page - Samsung semiconductor |
9 / 10 page KM6264B Family ELECTRONICS CMOS SRAM Revision. 0.0 Auust. 1996 9 FUNCTIONAL DESCRIPTION /CS1 H X L L L /WE X X H H L Mode Power Down Power Down Output Disable Read Write Current Mode Isb, Isb1 Isb, Isb1 Icc Icc Icc I/O Pin High-Z High-Z High-Z Dout Din /OE X X H L X CS2 X L H H H Notes(Write Cycle) 1. A write occurs during the overlap of a low /CS1, a high CS2 and a low /WE. A write begins at the latest transition among /CS1 going low, CS2 going high and /WE going low. A write ends at the earliest transition among /CS1 going high, CS2 going low and /WE going high, tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at /CS1, or /WE going high, tWR2 applied in case a write ends at CS2 going to low. TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC tCW(2) tWR2(4) tAW tWP(1) Address /CS1 /WE Data in Data out tDW Data Vailid tAS(3) High - Z High - Z DH t CS2 tCW(2) * X means don't care |
类似零件编号 - KM6264BLGI-10 |
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类似说明 - KM6264BLGI-10 |
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