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KM44C4105C 数据表(PDF) 8 Page - Samsung semiconductor

部件名 KM44C4105C
功能描述  4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out
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制造商  SAMSUNG [Samsung semiconductor]
网页  http://www.samsung.com/Products/Semiconductor
标志 SAMSUNG - Samsung semiconductor

KM44C4105C 数据表(HTML) 8 Page - Samsung semiconductor

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CMOS DRAM
KM44C4005C, KM44C4105C
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the
tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If
tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes the
tRCD
tRCD(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
tWCS
tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
tCWD
tCWD(min), tRWDtRWD(min), tAWDtAWD(min) and tCPWDtCPWD(min), then the cycle is a read-
modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
tRCH and tRRH must be satisfied for a read cycle.
These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write
cycle and read-modify-write cycles.
Operation within the
tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
In test mode read cycle, the values of
tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified values. These parame-
ters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet.
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
tASC
≥6ns, Assume tT = 2.0ns.
In order to hold the address latched by the first CAS going low, the parameter tCLCH must be met.
The last CASx edge to go low.
The last CASx edge to go high.
The first CASx edge to go low.
The first CASx edge to go high.
Output parameter is refrenced to corresponding CASx input.
The last rising CASx edge to next cycle
′s last rising CASx edge.
The last rising CASx edge to first falling CASx edge.
The first DQx controlled by the first CASx to go low.
The last DQx controlled by the last CASx to go high.
Each CASx must meet minimum pulse width.
The last falling CASx edge to the first rising CASx edge.
If
tRASS
≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed
within 64ms/32ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
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