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KM416V1004C-6 数据表(PDF) 1 Page - Samsung semiconductor |
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KM416V1004C-6 数据表(HTML) 1 Page - Samsung semiconductor |
1 / 35 page KM416C1004C, KM416C1204C CMOS DRAM KM416V1004C, KM416V1204C This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung ′ s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines. • Part Identification - KM416C1004C/C-L (5V, 4K Ref.) - KM416C1204C/C-L (5V, 1K Ref.) - KM416V1004C/C-L (3.3V, 4K Ref.) - KM416V1204C/C-L (3.3V, 1K Ref.) • Extended Data Out Mode operation (Fast Page Mode with Extended Data Out) • 2 CAS Byte/Word Read/Write operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early Write or output enable controlled write • JEDEC Standard pinout • Available in plastic SOJ 400mil and TSOP(II) packages • Single +5V ±10% power supply (5V product) • Single +3.3V ±0.3V power supply (3.3V product) Control Clocks VBB Generator Refresh Timer Refresh Control Refresh Counter Row Address Buffer Col. Address Buffer Row Decoder Column Decoder Lower Data out Buffer RAS UCAS LCAS W Vcc Vss DQ0 to DQ7 A0-A11 (A0 - A9) *1 A0 - A7 (A0 - A9) *1 Memory Array 1,048,576 x16 Cells SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 1M x 16Bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION FEATURES FUNCTIONAL BLOCK DIAGRAM • Refresh Cycles Part NO. VCC Refresh cycle Refresh period Normal L-ver C1004C 5V 4K 64ms 128ms V1004C 3.3V C1204C 5V 1K 16ms V1204C 3.3V • Performance Range Speed tRAC tCAC tRC tHPC Remark -45 45ns 13ns 69ns 16ns 5V/3.3V -5 50ns 15ns 84ns 20ns 5V/3.3V -6 60ns 17ns 104ns 25ns 5V/3.3V • Active Power Dissipation Speed 3.3V 5V 4K 1K 4K 1K -45 - - 550 825 -5 324 504 495 770 -6 288 468 440 715 Unit : mW Upper Data in Buffer Upper Data out Buffer Lower Data in Buffer DQ8 to DQ15 OE Note) *1 : 1K Refresh |
类似零件编号 - KM416V1004C-6 |
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类似说明 - KM416V1004C-6 |
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