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KM416V4000B 数据表(PDF) 8 Page - Samsung semiconductor

部件名 KM416V4000B
功能描述  4M x 16bit CMOS Dynamic RAM with Fast Page Mode
Download  35 Pages
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制造商  SAMSUNG [Samsung semiconductor]
网页  http://www.samsung.com/Products/Semiconductor
标志 SAMSUNG - Samsung semiconductor

KM416V4000B 数据表(HTML) 8 Page - Samsung semiconductor

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KM416V4000B, KM416V4100B
CMOS DRAM
NOTES
An initial pause of 200§Á is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the
tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only.
If
tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that
tRCD
tRCD(max).
tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh
or Vol.
tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical char-
acteristics only. If
tWCS
tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
tCWD
tCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the
tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
In test mode read cycle, the value of
tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
5.
6.
7.
8.
9.
10.
11.
12.
1.
2.
3.
4.
KM416V40(1)00B Truth Table
RAS
LCAS
UCAS
W
OE
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
Standby
L
H
H
X
X
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-


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