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KM416V256D 数据表(PDF) 5 Page - Samsung semiconductor |
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KM416V256D 数据表(HTML) 5 Page - Samsung semiconductor |
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5 / 8 page  KM416C256D, KM416V256D CMOS DRAM CAPACITANCE (TA=25¡É, VCC=5V or 3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A8] CIN1 - 5 pF Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ15] CDQ - 7 pF Test condition (5V device) : VCC=5.0V¡¾10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Parameter Symbol -5 -6 -7 Units Notes Min Max Min Max Min Max Random read or write cycle time tRC 90 110 130 ns Read-modify-write cycle time tRWC 132 152 177 ns Access time from RAS tRAC 50 60 70 ns 3,4,10 Access time from CAS tCAC 15 15 20 ns 3,4,5 Access time from column address tAA 25 30 35 ns 3,10 CAS to output in Low-Z tCLZ 0 0 0 ns 3 Output buffer turn-off delay tOFF 0 12 0 12 0 17 ns 6 Transition time (rise and fall) tT 3 50 3 50 3 50 ns 2 RAS precharge time tRP 30 40 50 ns RAS pulse width tRAS 50 10K 60 10K 70 10K ns RAS hold time tRSH 15 15 20 ns CAS hold time tCSH 50 60 70 ns CAS pulse width tCAS 15 10K 15 10K 20 10K ns RAS to CAS delay time tRCD 20 35 20 45 20 50 ns 4 RAS to column address delay time tRAD 15 25 15 30 15 35 ns 10 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 10 10 10 ns Column address set-up time tASC 0 0 0 ns 12 Column address hold time tCAH 10 10 15 ns 12 Column address to RAS lead time tRAL 25 30 35 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 0 ns 8 Write command set-up time tWCS 0 0 0 ns 7 Write command hold time tWCH 10 10 15 ns Write command pulse width tWP 10 10 15 ns Write command to RAS lead time tRWL 15 15 15 ns Write command to CAS lead time tCWL 13 15 15 ns 15 AC CHARACTERISTICS (0¡É¡ÂTA¡Â70¡É, See note 1,2) Test condition (3.3V device) : VCC=3.3V¡¾0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V *1 Note) *1 : 5V only |
类似零件编号 - KM416V256D |
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类似说明 - KM416V256D |
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