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BU2872AK 数据表(PDF) 3 Page - Rohm |
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BU2872AK 数据表(HTML) 3 Page - Rohm |
3 / 4 page 3 Standard ICs BU2872AK •Electrical characteristics (unless otherwise noted, Ta = 25°C, VDD = 5V, VSS = 0V, VDD-VEE = 30V) Parameter Symbol Min. Typ. Max. Unit Conditions Measurement circuit Supply current Input threshold voltage Input current Oscillation frequency Segment output current Grid output current Off level leakage current Output pull-down resistance LED output high level voltage LED output low level voltage 〈Serial transfer〉 Input data hold Input data setup Output data delay Input clock cycle Input clock "H" width IDD —— 5mA Pin 44 external 1000 pF, when oscillated Fig.1 VIN 1.5 — 3.5 V Pins 1 to 4, 6, 8, 9 to 13 Fig.5 IIN —— 10 µA Pins 1 to 4, 6, 8, 9 to 13 Fig.2 FOSC 130 200 300 kHz Pin 44 external 1000 pF Fig.4 IOseg 7 —— mA Fig.2 IOgrd 20 —— mA Fig.2 IOFF —— 10 µA Fig.2 RD 15 31 60 k Ω Fig.2 VOH 4.0 —— V Fig.3 VOL —— 1.0 V Fig.3 TSH 0.16 —— µs — TSS 0.16 —— µs — TD —— 0.3 µs — TSCYC 0.5 —— µs — — — — — T40 — 60 % — Pins 15 to 26, 28 to 31 VO = VDD – 2V ∗2 Pins 26, 28 to 37 VO = VDD – 2V ∗2 Pins 15 to 26, 28 to 37 VO = VDD – VEE Pins 15 to 26, 28 to 37 Pins 39 to 42 IO = 1mA Pins 39 to 42 IO = – 10mA Input clock cycle at minimum value ∗2 Each of the high withstanding voltage output pins, pins 26 and 28 to 31, outputs the segment output current when set to the segment output and the grid current when set to the grid output. •Measurement circuits VEE VDD OSC VSS 1000p A Fig.1 VEE VDD VSS n n = Test pin A V Fig.2 VEE VDD VSS n V n = Test pin I Fig.3 OSC 1000p Monitor G1 VEE VDD VSS Fig.4 VEE VDD VSS Fig.5 |
类似零件编号 - BU2872AK |
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类似说明 - BU2872AK |
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