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UC3825ADWTRG4 数据表(PDF) 2 Page - Texas Instruments |
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UC3825ADWTRG4 数据表(HTML) 2 Page - Texas Instruments |
2 / 18 page UC1823A,UC2823A, UC2823B, UC3823A,UC3823B,UC1825A, UC2825A,UC2825B,UC3825A,UC3825B SLUS334D − AUGUST 1995 − REVISED NOVEMBER 2008 www.ti.com 2 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The UC3825 CLOCK pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing. The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current limit comparator. “A” version parts have UVLO thresholds identical to the original UC3823 and UC3825. The “B” versions have UVLO thresholds of 16 V and 10 V, intended for ease of use in off-line applications. Consult the application note, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, (SLUA125) for detailed technical and applications information. ORDERING INFORMATION UVLO TA MAXIMUM DUTY CYCLE 9.2 V / 8.4 V 16 V / 10 V TA MAXIMUM DUTY CYCLE SOIC−16(1) (DW) PDIP−16 (N) PLCC−20(1) (Q) SOIC−16 (DW) PDIP−16 (N) PLCC−20(1) (Q) −40 °C to 85°C < 100% UC2823ADW UC2823AN UC2823AQ UC2823BDW UC2823BN − −40 °C to 85°C < 50% UC2825ADW UC2825AN UC2825AQ UC2825BDW UC2825BN − −0 °C to 70°C < 100% UC3823ADW UC3823AN UC3823AQ UC3823BDW UC3823BN − −0 °C to 70°C < 50% UC3825ADW UC3825AN UC3825AQ UC3825BDW UC3825BN UC3825BQ (1) The DW and Q packages are also available taped and reeled. Add TR suffix to the device type (i.e., UC2823ADWR). To order quantities of 1000 devices per reel for the Q package and 2000 devices per reel for the DW package. UVLO TA MAXIMUM DUTY CYCLE 9.2 V / 8.4 V TA MAXIMUM DUTY CYCLE CDIP−16 (J) LCCC−20 (L) −55 °C to 125°C < 100% UC1823AJ, UC1823AJ883B, UC1823AJQMLV UC1823AL, UC1823AL883B −55 °C to 125°C < 50% UC1825AJ, UC1825AJ883B, UC1825AJQMLV UC1825AL, UC1825AL883B, UC1825ALQMLV PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 INV NI EAOUT CLK/LEB RT CT RAMP SS VREF VCC OUTB VC PGND OUTA GND ILIM DW, J, OR N PACKAGES (TOP VIEW) 3 2 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 OUTB VC NC PGND OUTA EAOUT CLK/LEB NC RT CT Q OR L PACKAGES (TOP VIEW) NC = no connection |
类似零件编号 - UC3825ADWTRG4 |
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类似说明 - UC3825ADWTRG4 |
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