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EP3SE50 数据表(PDF) 43 Page - Altera Corporation |
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EP3SE50 数据表(HTML) 43 Page - Altera Corporation |
43 / 341 page Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–33 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 5. Compare the results of steps 2 and 4. The increase or decrease in delay must be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-output) of the PCB trace. The Quartus II software reports the timing with the conditions listed in Table 1–37 using Equation 1–1 on page 1–7. Figure 1–6 shows the circuit that is represented by the output timing of the Quartus II software. Figure 1–7 and Figure 1–8 show the circuit that is represented by the output timing of the Quartus II software for differential outputs with single and multiple external resistors, respectively. Figure 1–6. Output Delay Timing Report Setup for Single-Ended Outputs and Dedicated Differential Outputs (Note 1) Note to Figure 1–6: (1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay must be accounted for with IBIS model simulations. Figure 1–7. Output Delay Timing Report Setup for Differential Outputs with Single External Resistor Figure 1–8. Output Delay Timing Report Setup for Differential Outputs with Three External Resistor Output Buffer VTT VCCIO RD Outputn Outputp RT CL RS VMEAS Output GND GND RD RP VMEAS Non-Dedicated Differential Outputs VMEAS RS RS RD RP VMEAS Non-Dedicated Differential Outputs VMEAS |
类似零件编号 - EP3SE50 |
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类似说明 - EP3SE50 |
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