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TPD4S012 数据表(PDF) 3 Page - Texas Instruments |
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TPD4S012 数据表(HTML) 3 Page - Texas Instruments |
3 / 9 page V BUS GND D+ D– - ID TPD4S012 www.ti.com SLVS928A – MARCH 2009 – REVISED NOVEMBER 2009 CIRCUIT DIAGRAM TERMINAL FUNCTIONS TERMINAL TYPE DESCRIPTION DRY XXX NAME PIN NO. BALL NO. 1 A1 D+ ESD clamp Provides ESD protection to the high-speed differential data lines 2 B1 D– ESD clamp Provides ESD protection to the high-speed differential data lines 3 B2 ID ESD clamp Provides ESD protection to the high-speed differential data lines 4 A2 GND Pwr Ground 5 – N.C. – Not internally connected 6 C1, C2 VBUS ESD clamp ESD clamp for high-voltage tolerant VBUS line(s) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VBUS voltage tolerance VBUS pin –0.3 20 V IO voltage tolerance D+, D–, ID pins –0.3 6 V Tstg Storage temperature range –65 125 °C TA Operating free-air temperature range –40 85 °C IEC 61000-4-2 Contact Discharge D+, D–, ID ±10 kV IEC 61000-4-2 Air-Gap Discharge D+, D–, ID ±10 kV IEC 61000-4-2 Contact Discharge VBUS pin ±10 kV IEC 61000-4-2 Air-Gap Discharge VBUS pin ±9 kV Peak pulse power (tp = 8/20 μs) D+, D–, ID, VBUS pins 60 W Peak pulse current (tp = 8/20 μs) D+, D–, ID, VBUS pins 3 A Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TPD4S012 |
类似零件编号 - TPD4S012 |
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类似说明 - TPD4S012 |
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