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CDCEL913PWRG4 数据表(PDF) 7 Page - Texas Instruments

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部件名 CDCEL913PWRG4
功能描述  Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDCEL913PWRG4 数据表(HTML) 7 Page - Texas Instruments

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10 pF
LVCMOS
CDCE913
CDCEL913
1kW
1kW
LVCMOS
LVCMOS
CDCE913
CDCEL913
TypicalDriver
Impedance
~32 W
LineImpedance
Zo=50 W
Series
Termination
~18 W
CDCE913
CDCEL913
www.ti.com
SCAS849E – JUNE 2007 – REVISED MARCH 2010
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
CDCEL913 — LVCMOS PARAMETER for VDDOUT = 1.8 V – Mode
VDDOUT = 1.7 V, IOH = –0.1 mA
1.6
VOH
LVCMOS high-level output voltage
VDDOUT = 1.7 V, IOH = –4 mA
1.4
V
VDDOUT = 1.7 V, IOH = –8 mA
1.1
VDDOUT = 1.7 V, IOL = 0.1 mA
0.1
VOL
LVCMOS low-level output voltage
VDDOUT = 1.7 V, IOL = 4 mA
0.3
V
VDDOUT = 1.7 V, IOL = 8 mA
0.6
tPLH, tPHL
Propagation delay
PLL bypass
2.6
ns
tr/tf
Rise and fall time
VDDOUT = 1.8 V (20%–80%)
0.7
ns
tjit(cc)
Cycle-to-cycle jitter (6) (7)
1 PLL switching, Y2-to-Y3
80
110
ps
tjit(per)
Peak-to-peak period jitter(7)
1 PLL switching, Y2-to-Y3
100
130
ps
tsk(o)
Output skew(8) , See Table 2
fOUT = 50 MHz; Y1-to-Y3
50
ps
odc
Output duty cycle(9)
fVCO = 100 MHz; Pdiv = 1
45%
55%
SDA/SCL PARAMETER
VIK
SCL and SDA input clamp voltage
VDD = 1.7 V; II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD; VDD = 1.9 V
±10
mA
VIH
SDA/SCL input high voltage(10)
0.7 VDD
V
VIL
SDA/SCL input low voltage(10)
0.3 VDD
V
VOL
SDA low-level output voltage
IOL = 3 mA, VDD = 1.7 V
0.2 VDD
V
CI
SCL/SDA Input capacitance
VI = 0 V or VDD
3
10
pF
(6)
10000 cycles.
(7)
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).
(8)
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.
(9)
odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr)
(10) SDA and SCL pins are 3.3 V tolerant.
PARAMETER MEASUREMENT INFORMATION
Figure 1. Test Load
Figure 2. Test Load for 50-
Ω Board Environment
Copyright © 2007–2010, Texas Instruments Incorporated
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Product Folder Link(s): CDCE913 CDCEL913


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