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SN74AUC2G34DRLRG4 数据表(PDF) 1 Page - Texas Instruments

部件名 SN74AUC2G34DRLRG4
功能描述  DUAL BUFFER GATE
Download  15 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SN74AUC2G34DRLRG4 数据表(HTML) 1 Page - Texas Instruments

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FEATURES
1
2
3
4
5
6
1Y
V
CC
2Y
2A
GND
1A
DBVPACKAGE
(TOP VIEW)
1
2
3
4
5
6
1Y
V
CC
2Y
2A
GND
1A
DCKPACKAGE
(TOP VIEW)
1
2
3
4
5
6
1Y
V
CC
2Y
2A
GND
1A
DRLPACKAGE
(TOP VIEW)
1
2
3
4
5
6
1Y
V
CC
2Y
2A
GND
1A
YZPPACKAGE
(BOTTOM VIEW)
DESCRIPTION/ORDERING INFORMATION
SN74AUC2G34
DUAL BUFFER GATE
SCES514B – NOVEMBER 2003 – REVISED JANUARY 2007
• Available in the Texas Instruments
• Low Power Consumption, 10 µA at 1.8 V
NanoFree™ Package
• ±8-mA Output Drive at 1.8 V
• Optimized for 1.8-V Operation and Is 3.6-V I/O
• Latch-Up Performance Exceeds 100 mA Per
Tolerant to Support Mixed-Mode Signal
JESD 78, Class II
Operation
• ESD Protection Exceeds JESD 22
• I
off Supports Partial-Power-Down Mode
2000-V Human-Body Model (A114-A)
Operation
200-V Machine Model (A115-A)
• Sub-1-V Operable
1000-V Charged-Device Model (C101)
• Max t
pd of 1.6 ns at 1.8 V
This dual buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC2G34 performs the Boolean function Y = A in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
Reel of 3000
SN74AUC2G34YZPR
_ _ _U9_
0.23-mm Large Bump – YZP (Pb-free)
SOT-563 – DRL
Reel of 4000
SN74AUC2G34DRLR
U9_
–40°C to 85°C
SOT-23 – DBV
Reel of 3000
SN74AUC2G34DBVR
U34_
SC-70 – DCK
Reel of 3000
SN74AUC2G34DCKR
U9_
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
• = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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