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LM3S9L97-IQC80-C1T 数据表(PDF) 11 Page - Texas Instruments |
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LM3S9L97-IQC80-C1T 数据表(HTML) 11 Page - Texas Instruments |
11 / 1219 page List of Figures Figure 1-1. Stellaris ® LM3S9L97 Microcontroller High-Level Block Diagram ............................. 67 Figure 2-1. CPU Block Diagram ............................................................................................. 70 Figure 2-2. TPIU Block Diagram ............................................................................................ 78 Figure 5-1. JTAG Module Block Diagram ................................................................................ 89 Figure 5-2. Test Access Port State Machine ........................................................................... 92 Figure 5-3. IDCODE Register Format ..................................................................................... 98 Figure 5-4. BYPASS Register Format .................................................................................... 98 Figure 5-5. Boundary Scan Register Format ........................................................................... 99 Figure 6-1. Basic RST Configuration .................................................................................... 102 Figure 6-2. External Circuitry to Extend Power-On Reset ....................................................... 103 Figure 6-3. Reset Circuit Controlled by Switch ...................................................................... 103 Figure 6-4. Power Architecture ............................................................................................ 106 Figure 6-5. Main Clock Tree ................................................................................................ 109 Figure 7-1. Hibernation Module Block Diagram ..................................................................... 207 Figure 7-2. Using a Crystal as the Hibernation Clock Source ................................................. 210 Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode ................................................................................................................ 210 Figure 8-1. Internal Memory Block Diagram .......................................................................... 233 Figure 9-1. μDMA Block Diagram ......................................................................................... 271 Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 277 Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 279 Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 280 Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 282 Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 283 Figure 10-1. Digital I/O Pads ................................................................................................. 333 Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 334 Figure 10-3. GPIODATA Write Example ................................................................................. 335 Figure 10-4. GPIODATA Read Example ................................................................................. 335 Figure 11-1. GPTM Module Block Diagram ............................................................................ 385 Figure 11-2. 16-Bit Input Edge-Count Mode Example .............................................................. 392 Figure 11-3. 16-Bit Input Edge-Time Mode Example ............................................................... 393 Figure 11-4. 16-Bit PWM Mode Example ................................................................................ 394 Figure 11-5. Timer Daisy Chain ............................................................................................. 395 Figure 12-1. WDT Module Block Diagram .............................................................................. 433 Figure 13-1. Implementation of Two ADC Blocks .................................................................... 458 Figure 13-2. ADC Module Block Diagram ............................................................................... 458 Figure 13-3. ADC Sample Phases ......................................................................................... 463 Figure 13-4. Doubling the ADC Sample Rate .......................................................................... 463 Figure 13-5. Skewed Sampling .............................................................................................. 464 Figure 13-6. Internal Voltage Conversion Result ..................................................................... 465 Figure 13-7. External Voltage Conversion Result .................................................................... 466 Figure 13-8. Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 467 Figure 13-9. Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 468 Figure 13-10. Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 468 Figure 13-11. Internal Temperature Sensor Characteristic ......................................................... 469 Figure 13-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 472 11 June 15, 2010 Texas Instruments-Advance Information Stellaris® LM3S9L97 Microcontroller |
类似零件编号 - LM3S9L97-IQC80-C1T |
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类似说明 - LM3S9L97-IQC80-C1T |
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