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SN74LVTH125DBRE4 数据表(PDF) 6 Page - Texas Instruments |
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SN74LVTH125DBRE4 数据表(HTML) 6 Page - Texas Instruments |
6 / 17 page SN54LVTH125, SN74LVTH125 3.3V ABT QUADRUPLE BUS BUFFERS WITH 3STATE OUTPUTS SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION th tsu From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 6 V Open GND 500 Ω 500 Ω Data Input Timing Input 2.7 V 0 V 2.7 V 0 V 2.7 V 0 V tw Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL tPHL tPLH VOH VOH VOL VOL 2.7 V 0 V Input Output Control Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ 3 V 0 V VOL + 0.3 V VOH − 0.3 V ≈0 V 2.7 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Output Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6 V GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V Figure 1. Load Circuit and Voltage Waveforms |
类似零件编号 - SN74LVTH125DBRE4 |
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类似说明 - SN74LVTH125DBRE4 |
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