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CS51312GDR16 数据表(PDF) 1 Page - ON Semiconductor

部件名 CS51312GDR16
功能描述  Synchronous CPU Buck Controller for 12 V Only Applications
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

CS51312GDR16 数据表(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 3
1
Publication Order Number:
CS51312/D
CS51312
Synchronous CPU
Buck Controller for
12 V Only Applications
The CS51312 is a synchronous dual NFET Buck Regulator
Controller. It is designed to power the core logic of the latest high
performance CPUs and ASICs from a single 12 V input. It uses the
V2™ control method to achieve the fastest possible transient response
and best overall regulation. It incorporates many additional features
required to ensure the proper operation and protection of the CPU and
Power system. The CS51312 provides the industry’s most highly
integrated solution, minimizing external component count, total
solution size, and cost.
The CS51312 is specifically designed to power Intel’s Pentium® II
processor and includes the following features: 5−bit DAC with 1.2%
tolerance, Power−Good output, overcurrent hiccup mode protection,
overvoltage protection, VCC monitor, Soft Start, adaptive voltage
positioning, adaptive FET non−overlap time, and remote sense. The
CS51312 will operate over a 9.0 V to 20 V (VCC2) range using either
single or dual input voltage and is available in 16 lead narrow body
surface mount package.
Features
Synchronous Switching Regulator Controller for CPU VCORE
Dual N−Channel MOSFET Synchronous Buck Design
V2 Control Topology
200 ns Transient Loop Response
5−Bit DAC with 1.2% Tolerance
Hiccup Mode Overcurrent Protection
40 ns Gate Rise and Fall Times (3.3 nF Load)
65 ns Adaptive FET Non−Overlap Time
Adaptive Voltage Positioning
Power Good Output Monitors Regulator Output
5.0 V/12 V or 12 V−Only Operation
VCC Monitor Provides Undervoltage Lockout
OVP Output Monitors Regulator Output
Multifunctional COMP Pin Provides ENABLE, Soft Start, and
Hiccup Timing in Addition to Control Loop Compensation
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
CS51312GD16
SO−16
48 Units/Rail
CS51312GDR16
SO−16
2500 Tape & Reel
PIN CONNECTIONS
MARKING DIAGRAM
SO−16
D SUFFIX
CASE 751B
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
1
CS51312
AWLYWW
16
1
16
VCC2
VCC1
1
16
GATE(H)
VOUT
GND
VFB
GATE(L)
VID4
OVP
VID3
PWRGD
VID2
COFF
VID1
COMP
VID0


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