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CAT1640ZD2I25GT3 数据表(PDF) 11 Page - ON Semiconductor |
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CAT1640ZD2I25GT3 数据表(HTML) 11 Page - ON Semiconductor |
11 / 18 page 11 CAT1640, CAT1641 Doc No. MD-3012, Rev. D © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1640/41 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. Read Operations The READ operation for the CAT1640/41 is initiated in the same manner as the write operation with one exception, that R/ W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. SCL SDA 8TH BIT STOP NO ACK DATA OUT 89 SLAVE ADDRESS S A C K DATA N O A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T Figure 10. Immediate Address Read Timing |
类似零件编号 - CAT1640ZD2I25GT3 |
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类似说明 - CAT1640ZD2I25GT3 |
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