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MT46V64M4 数据表(PDF) 76 Page - Micron Technology |
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MT46V64M4 数据表(HTML) 76 Page - Micron Technology |
76 / 93 page PDF: 09005aef80768abb/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN 74 ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 DDR SDRAM Operations Figure 38: WRITE Burst Notes: 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. An uninterrupted burst of 4 is shown. 4. A10 is LOW with the WRITE command (auto precharge is disabled). DQS tDQSS (MAX) tDQSS (NOM) tDQSS (MIN) tDQSS DM DQ CK CK# Command WRITE NOP NOP Address Bank a, Col b NOP T0 T1 T2 T3 T2n DQS tDQSS DM DQ DQS DM DQ DI b DI b DI b Don’t Care Transitioning Data tDQSS |
类似零件编号 - MT46V64M4 |
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类似说明 - MT46V64M4 |
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