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MT46V64M4 数据表(PDF) 61 Page - Micron Technology |
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MT46V64M4 数据表(HTML) 61 Page - Micron Technology |
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61 / 93 page  PDF: 09005aef80768abb/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN 59 ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 DDR SDRAM Operations Figure 25: Extended Mode Register Definition Notes: 1. n is the most significant row address bit from Table 2 on page 2. 2. The reduced drive strength option is available only on Design Revision F and K. 3. The QFC# option is not supported. ACTIVE After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period) results in 2.7 clocks rounded to 3. This is reflected in Figure 26 on page 60, which covers any case where 2 < tRCD (MIN)/tCK ≤ 3 (Figure 26 also shows the same case for tRRD; the same procedure is used to convert other specification limits from time units to clock cycles). A row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. Operating Mode Reserved Reserved E3 0 – E4 0 – E1, E0 Valid – DLL Enable Disable A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Extended mode register (Ex) Address bus 97 6 5 4 3 8 21 0 1 E0 0 1 Drive Strength Normal Reduced E1 2 Operating Mode . . . An BA1 BA0 . . . n1 n + 1 n + 2 E6 0 – E7 0 – E8 0 – E9 0 – E5 0 – . . . 0 – En 0 – DS E2 3 0 – Mn + 1 0 1 0 1 Mode Register Definition Base mode register Extended mode register Reserved Reserved Mn + 2 0 0 1 1 DLL 0 1 0 |
类似零件编号 - MT46V64M4 |
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类似说明 - MT46V64M4 |
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