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ADT7476AARQZ 数据表(PDF) 10 Page - ON Semiconductor |
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ADT7476AARQZ 数据表(HTML) 10 Page - ON Semiconductor |
10 / 67 page ADT7476A http://onsemi.com 10 Serial Bus Interface Control of the ADT7476A is carried out using the serial system management bus (SMBus). The ADT7476A is connected to this bus as a slave device, under the control of a master controller. The ADT7476A has a 7-bit serial bus address. When the device is powered up with Pin 13 (PWM3/ADDREN) high, the ADT7476A has a default SMBus address of 0101110 or 0x2E. The read/write bit must be added to get the 8-bit address. If more than one ADT7476A is to be used in a system, each ADT7476A is placed in ADDR SELECT mode by strapping Pin 13 low on powerup. The logic state of Pin 14 then determines the device’s SMBus address. The logic of these pins is sampled on powerup. The device address is sampled on powerup and latched on the first valid SMBus transaction, more precisely on the low-to-high transition at the beginning of the eighth SCL pulse, when the serial bus address byte matches the selected slave address. The selected slave address is chosen using the ADDREN pin/ADDR SELECT pin. Any attempted changes in the address have no effect after this. Table 1. Hardwiring the ADT7476A SMBus Device Address Pin 13 State Pin 14 State Address 0 Low (10 kW to GND) 0101100 (0x2C) 0 High (10 kW pullup) 0101101 (0x2D) 1 Don’t care 0101110 (0x2E) Figure 14. Default SMBus Address = 0x2E ADT7476A 14 ADDRESS = 0x2E VCC ADDR SELECT 13 PWM3/ADDREN 10kW Figure 15. SMBus Address = 0x2C (Pin 14 = 0) ADT7476A 14 ADDRESS = 0x2C 13 10k ADDR SELECT PWM3/ADDREN W Figure 16. SMBus Address = 0x2D (Pin 14 = 1) ADT7476A 14 ADDRESS = 0x2D 13 VCC 10k ADDR SELECT PWM3/ADDREN W Figure 17. Unpredictable SMBus Address if Pin 13 is Unconnected DO NOT LEAVE ADDREN UNCONNECTED! CAN CAUSE UNPREDICTABLE ADDRESSES. ADT7476A 14 13 NC VCC 10k CARE SHOULD BE TAKEN TO ENSURE THAT PIN 13 (PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 13 FLOATING COULD CAUSE THE ADT7476A TO POWER UP WITH AN UNEXPECTED ADDRESS. NOTE THAT IF THE ADT7476A IS PLACED INTO ADDR SELECT MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATIVE FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO HANDLE THESE DUAL FUNCTIONS. ADDR SELECT PWM3/ADDREN W The ability to make hardwired changes to the SMBus slave address allows the user to avoid conflicts with other devices sharing the same serial bus, for example, if more than one ADT7476A is used in a system. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, which is defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first), plus a R/W bit, which determine the direction of the data transfer, that is, whether data is written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period. A low-to-high transition, when the clock is high, can be interpreted as a stop signal. The number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th |
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