ADT7473ARQZ-1RL datasheet(10/74 Pages) ONSEMI

部件名	ADT7473ARQZ-1RL

功能描述	dBCOOL Remote Thermal Monitor and Fan Control

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制造商	ONSEMI [ON Semiconductor]

网页	http://www.onsemi.com

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ADT7473

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10

Figure 16. Unpredictable SMBus Address if Pin 8

is Unconnected

DO NOT LEAVE ADDREN

UNCONNECTED! CAN

CAUSE UNPREDICTABLE

ADDRESSES.

ADT7473−1

4

8

NC

VCC

10kΩ

CARE SHOULD BE TAKEN TO ENSURE THAT PIN 8

(PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 8

FLOATING COULD CAUSE THE ADT7473-1 TO POWER UP WITH

AN UNEXPECTED ADDRESS.

NOTE THAT IF THE ADT7473-1 IS PLACED INTO ADDR SELECT

MODE, PINS 8 AND 4 CANNOT BE USED AS THE ALTERNATIVE

FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT

CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO

HANDLE THESE DUAL FUNCTIONS.

ADDR SELECT

PWM3/ADDREN

The ability to make hardwired changes to the SMBus

slave address allows the user to avoid conflicts with other

devices sharing the same serial bus, for example, if more

than one ADT7473−1 is used in a system.

Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the slave device. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period because a low−to−high

transition when the clock is high might be interpreted as a

stop signal. The number of data bytes that can be transmitted

over the serial bus in a single read or write operation is

limited only by what the master and slave devices can

handle.

When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the tenth clock pulse to assert a stop

condition. In read mode, the master device overrides the

acknowledge bit by pulling the data line high during the low

period before the ninth clock pulse; this is known as No

Acknowledge. The master takes the data line low during the

low period before the tenth clock pulse, and then high during

the tenth clock pulse to assert a stop condition.

Any number of bytes of data can be transferred over the

serial bus in one operation, but it is not possible to mix read

and write in one operation, because the type of operation is

determined at the beginning and cannot subsequently be

changed without starting a new operation.

In the ADT7473/ADT7473−1, write operations contain

either one or two bytes, and read operations contain one

byte. To write data to one of the device data registers or read

data from it, the address pointer register must be set so the

correct data register is addressed, and then data can be

written into that register or read from it. The first byte of a

write operation always contains an address that is stored in

the address pointer register. If data is written to the device,

the write operation contains a second data byte that is written

to the register selected by the address pointer register.

This write operation is shown in Figure 17. The device

address is sent over the bus, and then R/W is set to 0. This

is followed by two data bytes. The first data byte is the

address of the internal data register to be written to, which

is stored in the address pointer register. The second data byte

is the data to be written to the internal data register.

When reading data from a register, there are two

possibilities:

• If the ADT7473/ADT7473−1’s address pointer register

value is unknown or not the desired value, it must first

be set to the correct value before data can be read from

the desired data register. This is done by performing a

write to the ADT7473/ADT7473−1, but only the data

byte containing the register address is sent, because no

data is written to the register. This is shown in

Figure 18.

A read operation is then performed consisting of the

serial bus address, R/W bit set to 1, followed by the

data byte read from the data register. This is shown in

Figure 19.

• If the address pointer register is known to be already at

the desired address, data can be read from the

corresponding data register without first writing to the

address pointer register, as shown in Figure 19.

R/W

0

SCL

SDA

10

1

0

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

ADT7473/ADT7473−1

START BY

MASTER

19

1

ACK. BY

ADT7473/ADT7473−1

9

D7

D6

D5

D4

D3

D2

D1

D0

STOP BY

MASTER

1

9

SCL (CONTINUED)

SDA (CONTINUED)

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 3

DATA BYTE

ACK. BY

ADT7473/ADT7473−1

Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

类似零件编号 - ADT7473ARQZ-1RL

制造商	部件名	数据表	功能描述
ON Semiconductor	ADT7473ARQZ-1RL	627Kb / 73P	Remote Thermal Monitor and Fan Control April, 2015 ??Rev. 10
ON Semiconductor	ADT7473ARQZ-1RL	624Kb / 73P	Remote Thermal Monitor and Fan Control November, 2016 ??Rev. 11

More results

类似说明 - ADT7473ARQZ-1RL

制造商	部件名	数据表	功能描述
ON Semiconductor	ADT7473	1Mb / 74P	dbCOOL Remote Thermal Monitor and Fan Control October, 2011 ??Rev. 7
Analog Devices	ADT7467	1Mb / 80P	dBCool Remote Thermal Monitor and Fan Controller REV. 0
ON Semiconductor	ADT7475_1110	639Kb / 58P	dbCOOL Remote Thermal Monitor and Fan Controller October, 2011 ??Rev. 5
Analog Devices	ADT7473	1Mb / 76P	dBCool Remote Thermal Monitor and Fan Controller REV. A
ON Semiconductor	ADT7460	645Kb / 46P	dBCOOL Remote Thermal Monitor and Fan Controller June, 2010 ??Rev. 5
	ADT7475	654Kb / 58P	dBCOOL Remote Thermal Monitor and Fan Controller June, 2009 ??Rev. 4
	ADT7467	938Kb / 77P	dBCool Remote Thermal Monitor and Fan Controller January 2008 ??Rev. 3
Analog Devices	ADT7475	1Mb / 68P	dBCool Remote Thermal Monitor and Fan Controller REV. A
ON Semiconductor	ADT7473	624Kb / 73P	Remote Thermal Monitor and Fan Control November, 2016 ??Rev. 11
ON Semiconductor	ADT7473	627Kb / 73P	Remote Thermal Monitor and Fan Control April, 2015 ??Rev. 10