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ADT7461ARMZ-2R 数据表(PDF) 3 Page - ON Semiconductor

部件名 ADT7461ARMZ-2R
功能描述  짹1??Temperature Monitor with Series Resistance Cancellation
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

ADT7461ARMZ-2R 数据表(HTML) 3 Page - ON Semiconductor

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ADT7461
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3
PIN ASSIGNMENT
Pin No.
Mnemonic
Description
1
VDD
Positive Supply, 3.0 V to 5.5 V.
2
D+
Positive Connection to Remote Temperature Sensor.
3
D−
Negative Connection to Remote Temperature Sensor.
4
THERM
Open−drain output that can be used to turn a fan on/off or throttle a CPU clock in the event of an
overtemperature condition. Requires pullup to VDD.
5
GND
Supply Ground Connection.
6
ALERT/THERM2
Open−Drain Logic Output Used as Interrupt or SMBus Alert. This may also be configured as a
second THERM output. Requires pullup resistor.
7
SDATA
Logic Input/Output, SMBus Serial Data. Open−drain output. Requires pullup resistor.
8
SCLK
Logic Input, SMBus Serial Clock. Requires pullup resistor.
SMBus TIMING SPECIFICATIONS (Note 1)
Parameter
Limit at TMIN and TMAX
Unit
Description
fSCLK
400
kHz max
tLOW
1.3
ms min
Clock low period, between 10% points.
tHIGH
0.6
ms min
Clock high period, between 90% points.
tR
300
ns max
Clock/data rise time.
tF
300
ns max
Clock/data fall time.
tSU; STA
600
ns min
Start condition setup time.
tHD; STA (Note 2)
600
ns min
Start condition hold time.
tSU; DAT (Note 3)
100
ns min
Data setup time.
tHD; DAT
300
ns min
Data hold time.
tSU; STO (Note 4)
600
ns min
Stop condition setup time.
tBUF
1.3
ms min
Bus free time between stop and start conditions.
1. Guaranteed by design, but not production tested.
2. Time from 10% of SDATA to 90% of SCLK.
3. Time for 10% or 90% of SDATA to 10% of SCLK.
4. Time for 90% of SCLK to 10% of SDATA.
Figure 2. Serial Bus Timing
SCLK
SDATA
tR
tF
tLOW
tHD;DAT
tHD;STA
tHIGH
tSU;DAT
STOP START
STOP
START
tSU;STA
tSU;STO
tHD;STA
tBUF


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