ADT7462ACPZ-REEL datasheet(6/81 Pages) ONSEMI

部件名	ADT7462ACPZ-REEL

功能描述	Flexible Temperature, Voltage Monitor, and System Fan Controller

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制造商	ONSEMI [ON Semiconductor]

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ADT7462

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ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)

Parameter

Unit

Max

Typ

Min

Test Conditions / Comments

OPEN−DRAIN SERIAL BUS OUTPUT (SDA)

Output Low Voltage, VOL

IOUT = −3 mA, VCC = +3.3 V

0.4

V

High Level Output Leakage Current, IOH

VOUT = VCC

0.1

±1.0

mA

SERIAL BUS DIGITAL INPUTS (SDA AND SCL)

Input High Voltage, VIH

2.1

V

Input Low Voltage, VIL

0.8

V

Hysteresis

500

mV

DIGITAL INPUT LOGIC LEVELS (VID0 to VID6) AND THERM, TACH, GPIO, VR_HOT, SCSI_TERM)

Input High Voltage, VIH

Bit 3 and Bit 4 of Configuration Register 3 = 0

1.7

V

Input Low Voltage, VIL

Bit 3 and Bit 4 of Configuration Register 3 = 0

0.8

V

Input High Voltage, VIH (VID0 to VID6)

Bit 3 of Configuration Register 3 = 1

0.65

V

Input High Voltage, VIH (THERM)

Bit 4 of Configuration Register 3 = 1

2/3 VCCP1

V

Input Low Voltage, VIL

Bit 3 and Bit 4 of Configuration Register 3 = 1

0.4

V

Hysteresis

500

mV

DIGITAL INPUT CURRENTS

Input High Current, IIH

VIN = VCC

−1.0

mA

Input Low Current, IIL

VIN = 0

+1.0

mA

Input Capacitance (Note 3)

5.0

pF

SERIAL BUS TIMING (Note 3)

Clock Frequency

See Figure 2

400

kHz

Glitch Immunity, tSW

See Figure 2

50

ns

Bus Free Time

See Figure 2

1.3

ms

Start Setup Time, tSU;STA

See Figure 2

0.6

ms

Start Hold Time, tHD;STA

See Figure 2

0.6

ms

SCL Low Time, tLOW

See Figure 2

1.3

ms

SCL High Time, tHIGH

See Figure 2

0.6

ms

SCL, SDA Rise Time, tR

See Figure 2

1000

ns

SCL, SDA Fall Time, tF

See Figure 2

300

ns

Data Setup Time, tSU;DAT

See Figure 2

100

ns

Detect Clock Low Timeout

Can be optionally enabled

25

ms

1. All voltages are measured with respect to GND, unless otherwise specified. Typical values are at TA = 25°C and represent the most likely

parametric norm. Logic inputs accept input high voltages up to 5.0 V, even when the device is operating at supply voltages below 5.0 V. Timing

specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.

2. Unused digital inputs connected to GND.

3. Guaranteed by design, not production tested.

4. Note that this specification does not apply if Pin 26 (VBATT, +1.2V) is being measured in single−channel mode. See Figure 16 in the Typical

Performance Characteristics section for VBATT accuracy.

5. For Pin 23 and Pin 24 configured as +1.8V or +2.5V only, restricted conditions of VCC ≥ 3.3 V and +25°C ≤ TA ≤ +125°C apply.

Figure 2. Serial Bus Timing Diagram

SCL

SDA

PS

S

P

tSU;STO

tHD;STA

tSU;STA

tSU;DAT

tHD;DAT

tHD;STA

tHIGH

tBUF

tLOW

tR

tF

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