LTC3589HUJ-TRPBF datasheet(30/44 Pages) LINER

部件名	LTC3589HUJ-TRPBF

功能描述	8-Output Regulator with Sequencing and I2C

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制造商	LINER [Linear Technology]

网页	http://www.linear.com

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LTC3589

30

3589p

Figure 13. Initial Power-Up and LDO1 Undervoltage RSTO Timing

LDO1

RSTO

3589 F13

VIN 2.7V

1 SEC

>25μs

INITIAL POWER-UP

LDO1 UNDERVOLTAGE

14ms

Software Control Mode

Once a power-up sequence is completed each regulator

may be enabled and disabled individually by the system

as needed for power mode requirements. Setting the out-

put voltage enable command register bit OVEN[7] HIGH

disconnects each regulator from its enable pin so control

is solely through the OVEN command register. To enter

software control mode, set command bit OVEN[7] HIGH

and the desired enable bits in OVEN[6:0] HIGH. Any of the

regulators enabled in OVEN[6:0] will stay on regardless

of the state of their enable pins when OVEN[7] is HIGH.

Setting the regulator enable bits and the software control

bit in OVEN[7] may occur on the same I2C start-stop

sequence. A normal shutdown using PWR_ON, OVEN

register to 0x00 to ensure all regulators are shut off.

FAULT DETECTION, SHUTDOWN, AND REPORTING

The LTC3589 monitors VIN,outputrailvoltagesandinternal

die temperature. A warning condition is indicated when

VIN is less than 2.9V and when internal die temperature

approaches the thermal shutdown temperature. A fault

condition occurs when VIN is less than 2.6V, any regulator

output is 8% low for 14ms, or the internal die temperature

is HIGH. Warning and fault states are reported via the IRQ,

PGOOD, and RTSO pins. Speciﬁc fault states are read via the

I2C serial port status registers IRQSTAT and PGSTAT.

RSTO Pin Function

The RSTO (reset output) pin is an open drain output for

use as a power-on reset signal. It is pulled LOW at initial

power until LDO1 is within 8% of its target and the initial

one second start-up timer is ﬁnished. RSTO remains HIGH

during normal operation and will be pulled low if LDO1

loses regulation for more than 25μs or a pushbutton hard

reset is initiated.

Figure 13 shows a initial power up for the RSTO pin. If

VIN is not above its under voltage thresholds at the end

of the 1 second start up time, the IRQ pin will be pulled

LOW and an under voltage bit will be set in the IRQSTAT

status register.

OPERATION

PGOOD Pin and PGSTAT Status Register Function

Each LTC3589 regulator has an internal power good out-

put that is active whenever the regulators feedback pin is

closer than –8% (typical) from its input reference voltage.

If any of the internal power good signals indicate a low

voltage for longer than 25μs (typical), the PGOOD pin is

pulled LOW and the appropriate bit in the PGSTAT status

register (Table 14) is set.

Table 14. PGSTAT Read Only Register Bit Deﬁnitions

PGSTAT[BIT] VALUE

SETTING

00

1

LDO1_STBY Output Low

LDO1_STBY Output Good

10

1

Step-Down Switching Regulator 1 Output Low

Step-Down Switching Regulator 1 Output Good

20

1

Step-Down Switching Regulator 2 Output Low

Step-Down Switching Regulator 2 Output Good

30

1

Step-Down Switching Regulator 3 Output Low

Step-Down Switching Regulator 3 Output Good

40

1

Buck-Boost Regulator 4 Output Low

Buck-Boost Regulator 4 Output Good

50

1

LDO2 Output Low

LDO2 Output Good

60

1

LDO3 Output Low

LDO3 Output Good

70

1

LDO4 Output Low

LDO4 Output Good

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