LTC3589HUJ-PBF datasheet(40/44 Pages) LINER

部件名	LTC3589HUJ-PBF

功能描述	8-Output Regulator with Sequencing and I2C

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制造商	LINER [Linear Technology]

网页	http://www.linear.com

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LTC3589

40

3589p

APPLICATIONS INFORMATION

The LTC3589 is optimized to support several families

of advanced portable applications processors including

the Marvell PXA3xx and PXA168 xscale processors, the

Freescale i.MX family including the new i.MX51, the TI

OMAP processors utilizing their Smart reﬂex, and many

additional ARM processors.

PXA3XX Monahans Processor Support

The PXA3XX processors are hardcoded to communicate

with a PMIC at speciﬁc command register addresses in

order to power up the processor supply rails from the

low power state. The LTC3589 I2C device address and

command register addresses map to PXA3xx command

register sub-address requirements. The LTC3589 write

address is 0x68. The key command register addresses

for PXA3xx support are the Output Voltage Enable (OVEN)

register at address 0x10. VCC_APPS/A_EN is mapped

to OVEN bit 0 (enable step-down switching regulator 1).

VCC_SRAM/S_EN is mapped to OVEN bit 2 (enable step-

down switching regulator 3). The voltage change control

register (VCCR) at command register address 0x20 con-

trols the dynamic voltage select and go bits required to

command a voltage change and slew when coming out

of low voltage standby or sleep modes into run mode.

The dynamic target voltage (xxDTV[1,2]) registers map

to the mandatory command register addresses. The full

register map for the LTC3589 shown in Table 15 and Table

16 supports Monahans, hard-coded I2C commands for

start-of-day operation, voltage-change sequence, supply

enable, and return-to-D0 state sequence.

The LTC3589 does not speciﬁcally reference the Mo-

nahans SYS_EN and PWR_EN enable pins but supports

these signals with individual enable input pins EN[1-4]

and EN_LDO[2,3] that should be hard-wired to SYS_EN

or PWR_EN as required for proper system level power

sequencing.

The LTC3589 RSTO signal is used to drive the Monahans

hard reset signal nRESET and is based on the state of

the always-active regulator output LDO1_STBY and by a

pushbutton hard reset request. The release of the RSTO

output is delayed a minimum of 10ms as required or as

long as 1s when the LTC3589 is reset using its pushbut-

ton controller.

PXA16X Armada Processor Support

LTC3589 includes spare register bits that can be accessed

by the processor for setting and recalling hibernate and

resume operation.

The keep-alive function allow a step-down switching

regulator to maintain system memory during a hibernate

shutdown state of the Armada processor.

i.MX Processor Support

The LTC3589 has hardware features speciﬁcally designed

for the latest i.MX family of processors from Freescale

Semiconductor. The i.MX37 controls the VSTB input pin

of the LTC3589 to command transitions between the run

mode core voltage and the lower level standby voltage. The

run and standby voltage levels are initially programmed

in I2C command registers xxBTV1 and xxBTV2. When the

VSTB pin is asserted high all four dynamically controlled

output supply rails will slew to the xxBTV2 set point. When

xxBTV1 and xxBTV2 are set at the same value, as they are

by default, then no slewing occurs. This allows the single

VSTB pin to control any combination of the four DAC con-

trolled regulators to slew between two programmed output

voltages. When VSTB is de-asserted back to a zero value

the regulators slew back up to the xxBTV1 set point.

Earlier i.MX family processors such as the i.MX31 included

two VSTB pins used for controlling the regulator outputs

for a low voltage standby mode, nominal voltage run mode,

and a higher voltage overdrive mode. The LTC3589 can

be used with these processors using the VSTB input pin

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