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FAN4931 数据表(PDF) 9 Page - Fairchild Semiconductor |
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FAN4931 数据表(HTML) 9 Page - Fairchild Semiconductor |
9 / 11 page © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4931 • Rev. 1.0.0 9 Layout Considerations General layout and supply bypassing play major roles in high-frequency performance. Fairchild evaluation boards help guide high-frequency layout and aid in device testing and characterization. Follow the steps below as a basis for high-frequency layout: 1. Include 6.8μF and 0.01μF ceramic capacitors. 2. Place the 6.8μF capacitor within 0.75 inches of the power pin. 3. Place the 0.01μF capacitor within 0.1 inches of the power pin. 4. Remove the ground plane under and around the part, especially near the input and output pins, to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Refer to the evaluation board layouts shown in Figures 24-26 for more information. When evaluating only one channel, complete the following on the unused channel: 1. Ground the non-inverting input. 2. Short the output to the inverting input. Evaluation Board Information The following evaluation board is available to aid in the testing and layout of this device. Evaluation Board Description Products FAN4931-011 Single-Channel, Dual-Supply, 5 -Lead SC70 FAN4931IP5X Evaluation board schematics are shown in Figure 24; layouts are shown in Figures 25-26. Figure 24. Evaluation Board Schematic Board Layout Information Figure 25. Top Side Figure 26. Bottom Side |
类似零件编号 - FAN4931 |
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类似说明 - FAN4931 |
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