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LPC1758FBD80 数据表(PDF) 41 Page - NXP Semiconductors |
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LPC1758FBD80 数据表(HTML) 41 Page - NXP Semiconductors |
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41 / 835 page  UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 41 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control The PLL0 output frequency (when PLL0 is both active and connected) is given by: FCCO = (2 × M × FIN) / N PLL inputs and settings must meet the following: • FIN is in the range of 32 kHz to 50 MHz. • FCCO is in the range of 275 MHz to 550 MHz. The equation can be solved for other PLL parameters: M = (FCCO × N) / (2 × FIN) N = (2 × M × F IN) / FCCO FIN = (FCCO × N) / (2 × M) Allowed values for M: At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are allowed. This supports the entire useful range of both the main oscillator and the IRC. For lower frequencies, specifically when the RTC is used to clock PLL0, a set of 65 additional M values have been selected for supporting baud rate generation, CAN/USB operation, and obtaining integer MHz frequencies. These values are shown in Table 4–26. Table 25. PLL frequency parameter Parameter Description FIN the frequency of PLLCLKIN from the Clock Source Selection Multiplexer. FCCO the frequency of the PLLCLK (output of the PLL Current Controlled Oscillator) N PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG NSEL0 field + 1). N is an integer from 1 through 32. M PLL0 Multiplier value from the MSEL0 bits in the PLL0CFG register (PLL0CFG MSEL0 field + 1). Not all potential values are supported. See below. FREF PLL internal reference frequency, FIN divided by N. |
类似零件编号 - LPC1758FBD80 |
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类似说明 - LPC1758FBD80 |
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