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SC16C2552B 数据表(PDF) 10 Page - NXP Semiconductors

部件名 SC16C2552B
功能描述  5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

SC16C2552B 数据表(HTML) 10 Page - NXP Semiconductors

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SC16C2552B_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
10 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
made available at the user data interface D0 to D7. The user optionally compares the
received data to the initial transmitted data for verifying error-free operation of the UART
TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using
lower four bits of the Modem Status Register (MSR[3:0]) instead of the four Modem Status
Register bits 7:4. The interrupts are still controlled by the IER.
Fig 4.
Internal Loopback mode diagram
CTSA, CTSB
TRANSMIT
FIFO
REGISTERS
TXA, TXB
RECEIVE
SHIFT
REGISTER
RECEIVE
FIFO
REGISTERS
RXA, RXB
SC16C2552B
TRANSMIT
SHIFT
REGISTER
002aaa489
DATA BUS
AND
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
INTERRUPT
CONTROL
LOGIC
D0 to D7
IOR
IOW
RESET
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
RTSA, RTSB
DSRA, DSRB
DTRA, DTRB
RIA, RIB
(OP1A, OP1B)
CDA, CDB
(OP2A, OP2B)
MCR[4] = 1
XTAL2
XTAL1
A0 to A2
CS
CHSEL


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类似说明 - SC16C2552B

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