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SC16C2552B 数据表(PDF) 7 Page - NXP Semiconductors |
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SC16C2552B 数据表(HTML) 7 Page - NXP Semiconductors |
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7 / 38 page  SC16C2552B_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 12 February 2009 7 of 38 NXP Semiconductors SC16C2552B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 6.2 Internal registers The SC16C2552B provides two sets of internal registers (A and B) consisting of 13 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 4. The UART registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), a user accessible scratchpad register (SPR), and an Alternate Function Register (AFR). [1] The baud rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 1 for the register set (A/B) being accessed. 6.3 FIFO operation The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. The user can set the receive trigger level via FCR[7:6], but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. A time-out interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character, or the receive trigger interrupt is generated when RX FIFO level is equal to the program RX trigger value. 6.4 Time-out interrupts The interrupts are enabled by IER[3:0]. Care must be taken when handling these interrupts. Following a reset, if the transmitter interrupt is enabled, the SC16C2552B will issue an interrupt to indicate that the Transmit Holding Register is empty. The ISR register provides the current singular highest priority interrupt only. A condition can exist where a higher priority interrupt may mask the lower priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. Table 4. Internal registers decoding A2 A1 A0 Read mode Write mode General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR) 0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register Line Control Register 1 0 0 Modem Control Register Modem Control Register 1 0 1 Line Status Register n/a 1 1 0 Modem Status Register n/a 1 1 1 Scratchpad Register Scratchpad Register Baud rate register set (DLL/DLM, AFR)[1] 0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch 0 1 0 Alternate Function Register Alternate Function Register |
类似零件编号 - SC16C2552B |
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类似说明 - SC16C2552B |
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