SC16C2550BIA44 datasheet(6/43 Pages) NXP | 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

部件名	SC16C2550BIA44

功能描述	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

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制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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6 / 43 page

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

6 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

5.2 Pin description

Table 3.

Pin description

Symbol

Type

Description

HVQFN32 DIP40 PLCC44 LQFP48

A0

19

28

31

28

I

Address 0 select bit. Internal register address selection.

A1

18

27

30

27

I

Address 1 select bit. Internal register address selection.

A2

17

26

29

26

I

Address 2 select bit. Internal register address selection.

CSA

8

14

16

10

I

Chip Select A, B (active LOW). This function is associated

with individual channels, A through B. These pins enable data

transfers between the user CPU and the SC16C2550B for the

channel(s) addressed. Individual UART sections (A, B) are

addressed by providing a logic 0 on the respective CSA, CSB

pin.

CSB

9

15

17

11

I

D0

27

1

2

44

I/O

Data bus (bidirectional). These pins are the 8-bit, 3-state data

bus for transferring information to or from the controlling CPU.

D0 is the least signiﬁcant bit and the ﬁrst data bit in a transmit

or receive serial data stream.

D1

28

2

3

45

I/O

D2

29

3

4

46

I/O

D3

30

4

5

47

I/O

D4

31

5

6

48

I/O

D5

32

6

7

1

I/O

D6

1

7

8

2

I/O

D7

2

8

9

3

I/O

GND

13

20

22

17

I

Signal and power ground.

INTA

21

30

33

30

O

Interrupt A, B (3-state). This function is associated with

individual channel interrupts, INTA, INTB. INTA, INTB are

enabled when MCR bit 3 is set to a logic 1, interrupts are

enabled in the Interrupt Enable Register (IER) and is active

when an interrupt condition exists. Interrupt conditions include:

receiver errors, available receiver buffer data, transmit buffer

empty or when a modem status ﬂag is detected.

INTB

20

29

32

29

O

IOR

14

21

24

19

I

Read strobe (active LOW strobe). A logic 0 transition on this

pin will load the contents of an internal register deﬁned by

address bits A0 to A2 onto the SC16C2550B data bus

(D0 to D7) for access by external CPU.

IOW12

18

20

15

I

Write strobe (active LOW strobe). A logic 0 transition on this

pin will transfer the contents of the data bus (D0 to D7) from the

external CPU to an internal register that is deﬁned by address

bits A0 to A2.

OP2A

22

31

35

32

O

Output 2 (user-deﬁned). This function is associated with

individual channels, A through B. The state at these pin(s) are

deﬁned by the user and through MCR register bit 3. INTA, INTB

are set to the active mode and OP2 to logic 0 when MCR[3] is

set to a logic 1. INTA, INTB are set to the 3-state mode and

OP2 to a logic 1 when MCR[3] is set to a logic 0. See Table 18

“Modem Control Register bits description”, bit 3 (MCR[3]).

Since these bits control both the INTA, INTB operation and

OP2 outputs, only one function should be used at one time, INT

or OP2.

OP2B

7

13

15

9

O

类似零件编号 - SC16C2550BIA44

制造商	部件名	数据表	功能描述
NXP Semiconductors	SC16C2550BIA44	200Kb / 42P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 02-14 December 2004
NXP Semiconductors	SC16C2550BIA44	211Kb / 43P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 04-15 February 2007

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类似说明 - SC16C2550BIA44

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