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SC16C2550BIA44 数据表(PDF) 3 Page - NXP Semiconductors |
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SC16C2550BIA44 数据表(HTML) 3 Page - NXP Semiconductors |
3 / 43 page ![]() SC16C2550B_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 12 January 2009 3 of 43 NXP Semiconductors SC16C2550B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 4. Block diagram Fig 1. Block diagram of SC16C2550B TXA, TXB RXA, RXB SC16C2550B XTAL2 XTAL1 D0 to D7 IOR IOW RESET 002aaa595 DATA BUS AND CONTROL LOGIC REGISTER SELECT LOGIC A0 to A2 CSA CSB INTERRUPT CONTROL LOGIC INTA, INTB TXRDYA, TXRDYB RXRDYA, RXRDYB CLOCK AND BAUD RATE GENERATOR MODEM CONTROL LOGIC DTRA, DTRB RTSA, RTSB OP2A, OP2B CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB RECEIVE SHIFT REGISTER RECEIVE FIFO REGISTER TRANSMIT SHIFT REGISTER TRANSMIT FIFO REGISTER |
类似零件编号 - SC16C2550BIA44 |
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类似说明 - SC16C2550BIA44 |
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