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Si5365 数据表(PDF) 11 Page - Silicon Laboratories |
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Si5365 数据表(HTML) 11 Page - Silicon Laboratories |
11 / 50 page Si5317 Preliminary Rev. 0.15 11 LVCMOS Output Pins Rise/Fall Times tRF CLOAD = 20 pf See Figure 2 —25 — ns LOSn Trigger Window LOSTRIG From LVST CKIN to LOS —750 µs Time to Clear LOS Alarm tLOSCLR Measured from appearance of valid CKIN to of LOS alarm 90 — 220 ms Time to Clear LOL after LOS Cleared tCLRLOL fin unchanged and XA/XB stable. LOS to LOL —10 — ms PLL Performance Lock Time tLOCKHW RST with valid CKIN to LOL; BW = 100 Hz — 1.2 sec Closed Loop Jitter Peaking JPK — 0.05 0.1 dB Jitter Tolerance JTOL BW determined by BWSEL[1:0] 5000/ BW — — ns pk- pk Minimum Reset Pulse Width tRSTMIN 1— — µs Lock Time tLOCKMP Reset b to of LOL — 35 1000 ms Spurious Noise SPSPUR Max spur @ n x f3 (n > 1, n x f3 < 100 MHz) —— –75 dBc Table 4. AC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Units |
类似零件编号 - Si5365 |
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类似说明 - Si5365 |
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