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ADP8861DBCB-EVALZ 数据表(PDF) 4 Page - Analog Devices |
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ADP8861DBCB-EVALZ 数据表(HTML) 4 Page - Analog Devices |
4 / 40 page ADP8861 Rev. 0 | Page 4 of 40 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Output Overvoltage Protection VOVP Activation Level 5.8 V OVP Recovery Hysteresis 500 mV Thermal Shutdown Threshold TSD 150 °C Hysteresis TSD(HYS) 20 °C Isolation from Input to Output During Fault IOUTLKG VIN = 5.5 V, VOUT = 0 V, Bit nSTBY = 0 1.5 μA Time to Validate a Fault tFAULT 2 μs I2C INTERFACE Operating VDDIO Voltage VDDIO 5.5 V Logic Low Input2 VIL VIN = 2.5 V 0.5 V Logic High Input3 VIH VIN = 5.5 V 1.55 V I2C TIMING SPECIFICATIONS Guaranteed by design Delay from Reset Deassertion to I2C Access tRESET 20 μs SCL Frequency fSCL 400 kHz SCL High Time tHIGH 0.6 μs SCL Low Time tLOW 1.3 μs Setup Time Data tSU, DAT 100 ns Repeated Start tSU, STA 0.6 μs Stop Condition tSU, STO 0.6 μs Hold Time Data tHD, DAT 0 0.9 μs Start/Repeated Start tHD, STA 0.6 μs Bus Free Time (Stop and Start Conditions) tBUF 1.3 μs Rise Time (SCL and SDA) tR 20 + 0.1 CB 300 ns Fall Time (SCL and SDA) tF 20 + 0.1 CB 300 ns Pulse Width of Suppressed Spike tSP 0 50 ns Capacitive Load per Bus Line CB 400 pF 1 Current source matching is calculated by dividing the difference between the maximum and minimum currents from the sum of the maximum and minimum. 2 VIL is a function of the input voltage. See Figure 15 in the Typical Performance Characteristics section for typical values over operating ranges. 3 VIH is a function of the input voltage. See Figure 15 in the Typical Performance Characteristics section for typical values over operating ranges. I2C TIMING DIAGRAM SDA SCL S S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION Sr P S tLOW tR tHD, DAT tHIGH tSU, DAT tF tF tSU, STA tHD, STA tSP tSU, STO tBUF tR Figure 2. I2C Interface Timing Diagram |
类似零件编号 - ADP8861DBCB-EVALZ |
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类似说明 - ADP8861DBCB-EVALZ |
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