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Si3452B-B01-GM 数据表(PDF) 9 Page - Silicon Laboratories |
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Si3452B-B01-GM 数据表(HTML) 9 Page - Silicon Laboratories |
9 / 36 page Si3452/3 Rev. 1.0 9 Figure 1. I2C Timing Diagram Table 11. SMBus (I2C) Timing Specifications (see Figure 1) VDD = 3.0 to 3.6 V Description Symbol Test Conditions Min Typ Max Unit Serial bus clock frequency fSCL 0— 400 kHz SCL high time tSKH 600 — — ns SCL low time tSKL 1.3 — — μs SCL, SDA rise time tR_SCL 20 — 300 ns SCL, SDA fall time tF_SCL 20 — 150 ns Bus free time tBUF Between START and STOP conditions. 1.3 — — μs Start hold time tSTH Between START and first low SCL. 600 — — ns Start setup time tSTS Between SCL high and START condition. 600 — — ns Stop setup time tSPS Between SCL high and STOP condition. 600 — — ns Data hold time tDH 200 — — ns Data setup time tDS 200 — — ns Time from hardware or soft- ware reset until start of I2C traffic tRESET Reset to start condition — — 100 ms Delay from event to INT pin low or from clear-on-read to INT pin high tINT —— 5 ms Notes: 1. Not production tested (guaranteed by design). 2. All timing references measured at VIL and VIH. 3. The Si3452/3 will stretch (pull down on) SCK during the ACK time period if required. The maximum SCL stretching is 10 µsec; so, SCL only needs to be bidirectional for I2C bus speeds over 50 kHz. SCL D7 fSCL tR_SCL tF_SCL tSKH SDA tSKL tSTH tSPS D6 D5 D4 D3 D0 tDS tDH Start Bit Stop Bit tBUF |
类似零件编号 - Si3452B-B01-GM |
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类似说明 - Si3452B-B01-GM |
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