ISL29011IROZ-T7 datasheet(5/16 Pages) INTERSIL

部件名	ISL29011IROZ-T7

功能描述	Digital Ambient Light Sensor and Proximity Sensor with Interrupt Function

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制造商	INTERSIL [Intersil Corporation]

网页	http://www.intersil.com/cda/home

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5 / 16 page

5

FN6467.3

February 4, 2010

VIRLED

Voltage Head Room of IRDR Pin

VDD - 0.6

V

tr

Rise Time for IRDR Source Current

RLOAD = 15Ω at IRDR pin, 20% to 80%

35

ns

tf

Fall Time for IRDR Source Current

RLOAD = 15Ω at IRDR pin, 80% to 20%

10

ns

fIRLED1

IR LED Modulation Frequency

Freq = 0 (Note 8)

DC

kHz

fIRLED2

IR LED Modulation Frequency

Freq = 1 (Note 8)

360

kHz

ISUP (IRLED1) Supply Current of Proximity Sensing

IS<1:0> = 0, Freq = 0 (Note 8)

101

mA

ISUP (IRLED2) Supply Current of Proximity Sensing

IS<1:0> = 0, Freq = 1 (Note 8)

51

mA

Duty Cycle Duty Cycle of IR LED Modulation

50

%

PROX-IR

PROX

Differential ADC Output of IR and

Proximity Sensing With Object Far

Away to Provide No Reflection

IR and proximity sensing with Range 2 and Scheme 0;

15

Ω @ IRDR pin, IS<1:0> = 0, Freq = 0; E = 210 lux,

Sunlight.

1.0

%

NOTES:

5. VSUP is the common voltage to VDDD and VDDA.

6. 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count against an illuminance level

of 300 lux fluorescent light.

7. 850nm infrared LED is used in production test. The 850nm LED irradiance is calibrated to produce the same DATA_IR count against an illuminance

level of 210 lux sunlight at sea level.

8. See “Register Set” on page 8.

Electrical Specifications

VSUP(VDDD,VDDA) = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance, 16-bit ADC operation, unless otherwise specified.

(Continued)

PARAMETER

DESCRIPTION

CONDITION

MIN

TYP

MAX

UNIT

I2C Electrical Specifications

For SCL and SDA unless otherwise noted, VSUP(VDDD,VDDA) = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance,

16-bit ADC operation (Note 9).

PARAMETER

DESCRIPTION

CONDITION

MIN

TYP MAX UNIT

VI2C

Supply Voltage Range for I2C Interface

1.7

3.63

V

fSCL

SCL Clock Frequency

400

kHz

VIL

SCL and SDA Input Low Voltage

0.55

V

VIH

SCL and SDA Input High Voltage

1.25

V

Vhys

Hysteresis of Schmitt Trigger Input

0.05VDD

V

VOL

Low-level output voltage (open-drain) at 4mA sink

current

0.4

V

Ii

Input Leakage for each SDA, SCL pin

-10

10

µA

tSP

Pulse width of spikes that must be suppressed by

the input filter

50

ns

tAA

SCL Falling Edge to SDA Output Data Valid

900

ns

Ci

Capacitance for each SDA and SCL pin

10

pF

tHD:STA

Hold Time (Repeated) START Condition

After this period, the first clock pulse is

generated.

600

ns

tLOW

LOW Period of the SCL clock

Measured at the 30% of VDD crossing.

1300

ns

tHIGH

HIGH period of the SCL Clock

600

ns

tSU:STA

Set-up Time for a Repeated START Condition

600

ns

tHD:DAT

Data Hold Time

30

ns

tSU:DAT

Data Set-up Time

100

ns

tR

Rise Time of both SDA and SCL Signals

20 + 0.1xCb

ns

tF

Fall Time of both SDA and SCL Signals

20 + 0.1xCb

ns

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