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CDCE72010RGCTG4 数据表(PDF) 2 Page - Texas Instruments |
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CDCE72010RGCTG4 数据表(HTML) 2 Page - Texas Instruments |
2 / 73 page DESCRIPTION PFD Charge Pump P PR RII _ _II N N S SE E C C_ _II N N A Au ux xiilliia arry y IIn np pu utt VCXO/VCOIN EEPROM OutputDivider1 U0N U0P U1N U1P U2N U2P U3N U3P U4N U4P U5N U5P U6N U6P U7N U7P U8N U8P U9Nor AUXIN– U9P or AUXIN+ OutputDivider2 OutputDivider3 OutputDivider4 OutputDivider5 OutputDivider6 OutputDivider7 OutputDivider8 PLL_LOCK REF_SEL POWERDOWN RESET HOLD or MODE_SEL AUX_SEL SPI_MISO SPI_LE(CD1) SPI_CLK(CD2) SPI_MOSI(CD3) Interface &Control Feedback Divider CDCE72010 SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The following relationship applies to the dividers: Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M) The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filter components. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user definable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. The built-in synchronization latches ensure that all outputs are synchronized for very low output skew. All device settings, including output signaling, divider value selection, input selection, and many more, are programmable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the device settings. The device operates in a 3.3V environment and is characterized for operation from –40°C to +85°C. Figure 1. High Level Block Diagram of the CDCE72010 2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010 |
类似零件编号 - CDCE72010RGCTG4 |
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类似说明 - CDCE72010RGCTG4 |
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