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SN74AUC2G04 数据表(PDF) 1 Page - Texas Instruments

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部件名 SN74AUC2G04
功能描述  DUAL INVERTER GATE
Download  13 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SN74AUC2G04 数据表(HTML) 1 Page - Texas Instruments

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SN74AUC2G04
DUAL INVERTER GATE
SCES437A – APRIL 2003 – REVISED JUNE 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Available in the Texas Instruments
NanoStar
 and NanoFree Packages
D Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D Ioff Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max tpd of 1.7 ns at 1.8 V
D Low Power Consumption, 10 µA at 1.8 V
D ±8-mA Output Drive at 1.8 V
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This dual inverter is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC2G04 performs the Boolean function Y = A.
NanoStar
 and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
–40 C to 85 C
NanoStar
 – WCSP (DSBGA)
0.23-mm Large Bump – YEP
Tape and reel
SN74AUC2G04YEPR
_ _ _UC_
–40
°C to 85°C
NanoFree
 – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Tape and reel
SN74AUC2G04YZPR
_ _ _UC_
SOT (SOT-23) – DBV
Tape and reel
SN74AUC2G04DBVR
U04_
SOT (SC-70) – DCK
Tape and reel
SN74AUC2G04DCKR
UC_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
Copyright
 2003, Texas Instruments Incorporated
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
6
5
4
1A
GND
2A
1Y
VCC
2Y
3
2
1
4
5
6
2A
GND
1A
2Y
VCC
1Y
YEP OR YZP PACKAGE
(BOTTOM VIEW)
NanoStar and NanoFree are trademarks of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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