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PSMN5R0-30YL 数据表(PDF) 3 Page - NXP Semiconductors |
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PSMN5R0-30YL 数据表(HTML) 3 Page - NXP Semiconductors |
3 / 14 page ![]() PSMN5R0-30YL_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 4 January 2010 3 of 14 NXP Semiconductors PSMN5R0-30YL N-channel TrenchMOS logic level FET Fig 1. Continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 003aac553 0 20 40 60 80 100 0 50 100 150 200 Tmb (°C) ID (A) Tmb (°C) 0 200 150 50 100 03aa16 40 80 120 Pder (%) 0 003aac588 10 -1 1 10 10 2 10 3 10 -1 1 10 10 2 VDS (V) ID (A) 100 μs 10 μs 100 ms 10 ms 1 ms Limit RDSon = VDS / ID DC |
类似零件编号 - PSMN5R0-30YL |
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类似说明 - PSMN5R0-30YL |
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