PSMN5R0-30YL datasheet(2/14 Pages) NXP | N-channel TrenchMOS logic level FET

部件名	PSMN5R0-30YL

功能描述	N-channel TrenchMOS logic level FET

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制造商	NXP [NXP Semiconductors]

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PSMN5R0-30YL_3

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Product data sheet

Rev. 03 — 4 January 2010

2 of 14

NXP Semiconductors

PSMN5R0-30YL

N-channel TrenchMOS logic level FET

2.

Pinning information

3.

Ordering information

4.

Limiting values

Table 2.

Pinning information

Symbol

Description

Simplified outline

Graphic symbol

1S

source

SOT669 (LFPAK)

2S

source

3S

source

4G

gate

mb

D

mounting base; connected to

drain

mb

1234

S

D

G

mbb076

Table 3.

Ordering information

Type number

Package

Name

Description

Version

PSMN5R0-30YL

LFPAK

plastic single-ended surface-mounted package (LFPAK); 4 leads

SOT669

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

VDS

drain-source voltage

Tj ≥ 25 °C; Tj ≤ 175 °C

-

30

V

VDGR

drain-gate voltage

Tj ≥ 25 °C; Tj ≤ 175 °C; RGS =20kΩ

-30

V

VGS

gate-source voltage

-20

20

V

ID

drain current

VGS =10V; Tmb = 100 °C; see Figure 1

-64

A

VGS =10V; Tmb =25°C; see Figure 1

-91

A

IDM

peak drain current

tp ≤ 10 µs; pulsed; Tmb =25°C; see Figure 3

-336

A

Ptot

total power dissipation

Tmb =25°C; see Figure 2

-61

W

Tstg

storage temperature

-55

175

°C

Tj

junction temperature

-55

175

°C

Source-drain diode

IS

source current

Tmb =25°C

-

84

A

ISM

peak source current

tp ≤ 10 µs; pulsed; Tmb =25°C

-

336

A

Avalanche ruggedness

EDS(AL)S

non-repetitive

drain-source avalanche

energy

VGS =10V; Tj(init) =25°C; ID =84A; Vsup ≤ 30 V;

RGS =50 Ω; unclamped

-32

mJ

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