74LVCH16374ABQ datasheet(10/19 Pages) NXP

部件名	74LVCH16374ABQ

功能描述	16-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state

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制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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10 / 19 page

74LVC_LVCH16374A_7

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Product data sheet

Rev. 07 — 23 March 2010

10 of 19

NXP Semiconductors

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 7.

Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency

001aaa256

nCP input

nQn output

tPHL

tPLH

tW

VOH

VI

GND

VOL

VM

1/fmax

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable performance.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 8.

Data set-up and hold times for the nDn input to the nCP input

001aaa257

GND

th

tsu

th

tsu

VM

VI

VOH

VOL

VI

nQn output

nCP input

nDn input

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制造商	部件名	数据表	功能描述
NXP Semiconductors	74LVCH16374A	82Kb / 10P	16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs 3-State 1998 Mar 17
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