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74LVCH2T45 数据表(PDF) 4 Page - NXP Semiconductors |
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74LVCH2T45 数据表(HTML) 4 Page - NXP Semiconductors |
4 / 32 page 74LVC_LVCH2T45_3 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 19 January 2010 4 of 32 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The input circuit of the data I/O is always active. [3] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. Fig 5. Pin configuration SOT996-2 (XSON8U) Fig 6. Pin configuration SOT902-1 (XQFN8U) 001aaj617 74LVC2T45 74LVCH2T45 Transparent top view 8 7 6 5 1 2 3 4 VCC(A) 1A 2A GND VCC(B) 1B 2B DIR 001aai906 1A 2B VCC(A) 2A 1B DIR Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC2T45 74LVCH2T45 Table 3. Pin description Symbol Pin Description SOT765-1, SOT833-1 and SOT996-2 SOT902-1 VCC(A) 1 7 supply voltage A (port A and DIR) 1A 2 6 data input or output 2A 3 5 data input or output GND 4 4 ground (0 V) DIR 5 3 direction control 2B 6 2 data input or output 1B 7 1 data input or output VCC(B) 8 8 supply voltage B (port B) Table 4. Function table[1] Supply voltage Input Input/output[2] VCC(A), VCC(B) DIR nA nB 1.2 V to 5.5 V L nA = nB input 1.2 V to 5.5 V H input nB = nA GND[3] X Z Z |
类似零件编号 - 74LVCH2T45 |
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类似说明 - 74LVCH2T45 |
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