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74LVC3G17DP 数据表(PDF) 8 Page - NXP Semiconductors |
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74LVC3G17DP 数据表(HTML) 8 Page - NXP Semiconductors |
8 / 18 page 74LVC3G17_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 6 June 2008 8 of 18 NXP Semiconductors 74LVC3G17 Triple non-inverting Schmitt trigger with 5 V tolerant input Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Load circuitry for switching times VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 10. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 k Ω open GND 2 × VCC 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6 V 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6 V 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open GND 2 × VCC |
类似零件编号 - 74LVC3G17DP |
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类似说明 - 74LVC3G17DP |
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