74AUP2G80GT datasheet(1/20 Pages) NXP

部件名	74AUP2G80GT

功能描述	Low-power dual D-type flip-flop; positive-edge trigger

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制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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1.

General description

The 74AUP2G80 provides the dual positive-edge triggered D-type ﬂip-ﬂop. Information on

the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock

transition for predictable operation.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

VCC range from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial power-down applications using IOFF.

The IOFF circuitry disables the output, preventing a damaging backﬂow current through the

device when it is powered down.

2.

Features

I Wide supply voltage range from 0.8 V to 3.6 V

I High noise immunity

I Complies with JEDEC standards:

N JESD8-12 (0.8 V to 1.3 V)

N JESD8-11 (0.9 V to 1.65 V)

N JESD8-7 (1.2 V to 1.95 V)

N JESD8-5 (1.8 V to 2.7 V)

N JESD8-B (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E Class 3A exceeds 5000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Low static power consumption; ICC = 0.9 µA (maximum)

I Latch-up performance exceeds 100 mA per JESD78 Class II

I Inputs accept voltages up to 3.6 V

I Low noise overshoot and undershoot < 10 % of VCC

I IOFF circuitry provides partial Power-down mode operation

I Multiple package options

I Speciﬁed from −40 °Cto+85 °C and −40 °C to +125 °C

74AUP2G80

Low-power dual D-type ﬂip-ﬂop; positive-edge trigger

Rev. 04 — 2 June 2008

Product data sheet

类似零件编号 - 74AUP2G80GT

制造商	部件名	数据表	功能描述
NXP Semiconductors	74AUP2G80GT	94Kb / 18P	Low-power dual D-type flip-flop; positive-edge trigger Rev. 01-25 August 2006
NXP Semiconductors	74AUP2G80GT	95Kb / 18P	Low-power dual D-type flip-flop; positive-edge trigger Rev. 02-1 August 2007
Nexperia B.V. All right...	74AUP2G80GT	279Kb / 19P	Low-power dual D-type flip-flop; positive-edge trigger Rev. 11 - 7 December 2020

制造商	部件名	数据表	功能描述
NXP Semiconductors	74AUP2G80	95Kb / 18P	Low-power dual D-type flip-flop; positive-edge trigger Rev. 02-1 August 2007
NXP Semiconductors	74AUP2G79	114Kb / 21P	Low-power dual D-type flip-flop; positive-edge trigger Rev. 04-30 June 2009
Nexperia B.V. All right...	74AUP2G79-Q100	235Kb / 15P	Low-power dual D-type flip-flop; positive-edge trigger
NXP Semiconductors	74AUP2G80	94Kb / 18P	Low-power dual D-type flip-flop; positive-edge trigger Rev. 01-25 August 2006
Nexperia B.V. All right...	74AUP2G79	279Kb / 19P	Low-power dual D-type flip-flop; positive-edge trigger Rev. 11 - 3 December 2020
Nexperia B.V. All right...	74AUP2G80	279Kb / 19P	Low-power dual D-type flip-flop; positive-edge trigger Rev. 11 - 7 December 2020
NXP Semiconductors	74AUP1G79	97Kb / 20P	Low-power D-type flip-flop; positive-edge trigger Rev. 01-12 September 2005
	74AUP1G79	113Kb / 20P	Low-power D-type flip-flop; positive-edge trigger Rev. 03-3 August 2009
	74AUP1G80	103Kb / 18P	Low-power D-type flip-flop; positive-edge trigger Rev. 01-20 October 2006
Nexperia B.V. All right...	74AUP1G79	305Kb / 21P	Low-power D-type flip-flop; positive-edge trigger Rev. 8 - 24 January 2022