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74ABT841PW 数据表(PDF) 3 Page - NXP Semiconductors |
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74ABT841PW 数据表(HTML) 3 Page - NXP Semiconductors |
3 / 15 page 74ABT841_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 25 March 2010 3 of 15 NXP Semiconductors 74ABT841 10-bit bus interface latch; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 4. Pin configuration 74ABT841 OE VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 D9 Q9 GND LE 001aae910 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) D0 to D9 2, 3, 4, 5, 6, 7, 8, 9,10, 11 data input GND 12 ground (0 V) LE 13 latch enable input (active falling edge) Q0 to Q9 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 data output VCC 24 positive supply voltage |
类似零件编号 - 74ABT841PW |
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类似说明 - 74ABT841PW |
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