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74ABT543APW 数据表(PDF) 4 Page - NXP Semiconductors |
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74ABT543APW 数据表(HTML) 4 Page - NXP Semiconductors |
4 / 15 page 74ABT543A_3 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 26 January 2010 4 of 15 NXP Semiconductors 74ABT543A Octal latched transceiver with dual enable; 3-state 6. Functional description 6.1 Function table [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA); L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA); ↑ = LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA); NC = no change; X = don’t care; Z = high-impedance OFF-state. 6.2 Description The 74ABT543A contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the A-to-B latch enable (LEAB) input and the A-to-B output enable (OEAB) input are all LOW, the A-to-B path is transparent. A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-state B output buffers are active and display the data present at the outputs of the A latches. Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs. Table 3. Function selection[1] Input Output Status OEXX EXX LEXX An or Bn Bn or An H XXXZ disabled XH XXZ L ↑ L h Z disabled + latch lZ LL ↑ h H latch + display lL L L L H H transparent LL L L H X NC hold |
类似零件编号 - 74ABT543APW |
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类似说明 - 74ABT543APW |
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