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HY5W6B6DLFP-PE 数据表(PDF) 8 Page - Hynix Semiconductor

部件名 HY5W6B6DLFP-PE
功能描述  4Banks x1M x 16bits Synchronous DRAM
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

HY5W6B6DLFP-PE 数据表(HTML) 8 Page - Hynix Semiconductor

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Rev. 0.1 / Feb. 2004
8
Preliminary
HY5W6B6DLF(P)-xE
4Banks x 1M x 16bits Synchronous DRAM
Power Up and Initialization
Like a Synchronous DRAM, Mobile SDR must be powered up and initialized in a predefined manner. Power must be
applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial
pause of 200 usec is required. And a precharge all command will be issued to the Mobile SDR. Then, 8 or more Auto
refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will
be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register
set command will be issued to program specific mode of self refresh operation(PASR). The following these cycles, the
Mobile SDR is ready for normal opeartion.
Programming the registers
Mode Register
The mode register contains the specific mode of operation of the Mobile SDR. This register includes the selection of a
burst length(1, 2, 4, 8, Full Page), a cas latency(1, 2 or 3), a burst type. The mode register set must be done before
any activate command after the power up sequence. Any contents of the mode register be altered by re-programming
the mode register through the execution of mode register set command.
Extended Mode Register
The extended mode register contains the specific features of self refresh opeartion of the Mobile SDR. This register
includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended mode register set
must be done before any activate command after the power up sequence. Any contents of the mode register be altered
by re-programming the mode register through the execution of extended mode register set command.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by
activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects
the bank, and the value on the A0-A11 selects the row. This row remains active for column access until a precharge
command is issued to that bank. Read and write opeartions can only be initiated on this activated bank after the min-
imum tRCD time is passed from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and
deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A7-A0 address inputs select
the sarting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Pre-
charge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not
selected, the row will remain active for subsequent accesses.
The length of burst and the CAS latency will be determined by the values programmed during the MRS command.
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE
and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A7-A0 address inputs select
the starting column location. The value on input A10 determines whether or not Auto Precharge is used.
If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Pre-
charge is not selected, the row will remain active for subsequent accesses.


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