Rev 1.0 / Jan. 2007

35

11

512Mbit (32Mx16bit) Mobile SDR Memory

HY5S7B6LF(P) Series

WRITE to READ

The preceding burst write operation can be aborted and a new burst read operation can be started by inputting a new

read command in the write cycle. The data of the read command (READ) is output after the lapse of the /CAS latency.

The preceding write operation (WRIT) writes only the data input before the read command.

The data bus must go into a high-impedance state at least one cycle before output of the latest data.

Note:

1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the

preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of

a burst write, data will continue to be written until one clock before the read command is executed.

2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is

necessary to separate the two commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided

that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock

before the read command is executed (as in the case of the same bank and the same address).

CLK

Don't Care

DQ

WRITE

READ

Command

BA, Col

b

Address

DQ

b0

b1

n0

BL = 4

n1

b0

b1

BL = 4

CL = 3

BA, Col

n

CL = 2

n0

n1