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HY5S5B6GLF-S 数据表(PDF) 37 Page - Hynix Semiconductor

部件名 HY5S5B6GLF-S
功能描述  256Mbit (16Mx16bit) Mobile SDR Memory
Download  52 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

HY5S5B6GLF-S 数据表(HTML) 37 Page - Hynix Semiconductor

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Rev 1.0 / Apr. 2006
37
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto
Precharge was not activated). When the precharge command is executed for the same bank as the write command
that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is
unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL. To follow a
WRITE without truncating the WRITE burst, tDPL should be met as shown in Fig.
Non-Interrupting Write to Precharge
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure.
Note that only data-inthat are registered prior to the tDPL period are written to the internal array, and any subsequent
data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent com-
mand to the same bank cannot be issued until tRP is met.
Interrupting Write to Precharge
CLK
WRITE
PRE
Command
BA, Col
b
Address
DQ
DI
b0
DIO
b2
BL = 4
DI
b1
CL = 2 or 3
tDPL
DI
b3
CLK
DQ
WRITE
PRE
Command
BA, Col
b
Address
DI
b0
DIO
b2
BL = 4
DI
b1
CL = 2 or 3
tDPL


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