数据搜索系统,热门电子元器件搜索
  Chinese  ▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

HY5PS121621CFP-S6I 数据表(PDF) 36 Page - Hynix Semiconductor

部件名 HY5PS121621CFP-S6I
功能描述  512Mb DDR2 SDRAM
Download  38 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

HY5PS121621CFP-S6I 数据表(HTML) 36 Page - Hynix Semiconductor

Back Button HY5PS121621CFP-S6I Datasheet HTML 30Page - Hynix Semiconductor HY5PS121621CFP-S6I Datasheet HTML 31Page - Hynix Semiconductor HY5PS121621CFP-S6I Datasheet HTML 32Page - Hynix Semiconductor HY5PS121621CFP-S6I Datasheet HTML 33Page - Hynix Semiconductor HY5PS121621CFP-S6I Datasheet HTML 34Page - Hynix Semiconductor HY5PS121621CFP-S6I Datasheet HTML 35Page - Hynix Semiconductor HY5PS121621CFP-S6I Datasheet HTML 36Page - Hynix Semiconductor HY5PS121621CFP-S6I Datasheet HTML 37Page - Hynix Semiconductor HY5PS121621CFP-S6I Datasheet HTML 38Page - Hynix Semiconductor  
Zoom Inzoom in Zoom Outzoom out
 36 / 38 page
background image
Rev. 0.8 / Oct. 2007
36
1HY5PS12421C(L)FP-xI
1HY5PS12821C(L)FP-xI
1HY5PS121621C(L)FP-xI
24. tWTR is at least two clocks (2*tCK) independent of operation frequency.
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal
crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a
rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing
VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between VIL(dc)max and VIH(dc) min.
26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal
crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a
rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing
VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between VIL(dc) max and VIH(dc) min.
27. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at
the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition,
CKE may not transition from its valid level during the time period of tIS + 2*tCK + tIH.
DQS
VDDQ
VIH(ac) min
VIH(dc) min
tIH
tIS
DQS
VREF(dc)
VSS
VIL(dc)max
VIL(ac)max
tIH
tIS


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38 


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn