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HY5PS121621CFP-S6I 数据表(PDF) 18 Page - Hynix Semiconductor

部件名 HY5PS121621CFP-S6I
功能描述  512Mb DDR2 SDRAM
Download  38 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

HY5PS121621CFP-S6I 数据表(HTML) 18 Page - Hynix Semiconductor

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Rev. 0.8 / Oct. 2007
18
1HY5PS12421C(L)FP-xI
1HY5PS12821C(L)FP-xI
1HY5PS121621C(L)FP-xI
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
= CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD),
tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
mA
Note:
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V
(exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade)
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
4. IDD parameters are specified with ODT disabled.
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
with all combinations of EMRS bits 10 and 11.
6. Definitions for IDD
LOW is defined as Vin £ VILAC(max)
HIGH is defined as Vin Š VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.


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